EU launches 2nd phase of Chips Act with €12B to boost local manufacturing

On July 27, 2026 (Brussels time), the European Commission officially announced the second phase of the European Chips Act (Chips Act Phase 2), investing €12 billion over the next three years to build two advanced process pilot lines, set up a special fund for semiconductor talent, and fund R&D of key technologies below the 2nm node. This is another major move after the first phase of the Chips Act (total investment of ~€43 billion) in 2023, marking the EU's shift from 'subsidy for plant construction' to 'technology breakthroughs and talent reserve' in semiconductor self-reliance.

Phase 2 focuses on three core areas

According to Thierry Breton, EU Commissioner for the Internal Market, at a Brussels press conference, Phase 2 revolves around three main axes: 'advanced process pilot lines,' 'quantum and heterogeneous integration R&D,' and 'semiconductor talent cultivation.'

Advanced process pilot lines: Two 3nm/2nm hybrid bonding pilot lines will be built in Dresden, Germany, and Grenoble, France, for early process verification and yield improvement, avoiding the high trial-and-error costs of direct commercial fab construction. The pilot lines are expected to begin production in 2028 and will be open to European design companies and small/mid-sized innovative firms.
Quantum and heterogeneous integration R&D: €2 billion will be invested to fund breakthroughs in silicon-based spin qubit quantum chips and chiplet heterogeneous integration technology, aiming to secure a leading position in next-generation computing architectures.
Special talent program: A 'European Semiconductor Academy' will be established in partnership with Infineon, NXP, STMicroelectronics, and several technical universities. The goal is to train 50,000 senior engineers and 20,000 technicians by 2030, bridging the EU's annual semiconductor talent gap of about 12,000 people.

Strategic intent to reduce reliance on Asia

According to the Semiconductor Supply Chain Risk Assessment Report released by the European Commission, Europe remains highly dependent on Asian-made chips, especially in advanced processes below 28nm, where over 80% of supply comes from TSMC and Samsung. Although Intel and TSMC have previously announced fab projects in Germany and France, progress has been repeatedly delayed due to cost overruns and infrastructure bottlenecks. Phase 2 adopts a 'public pilot line' approach led by European local organizations and research institutions, reducing dependence on the construction progress of foreign-invested fabs.

'We must master advanced manufacturing capabilities; we cannot entrust our digital sovereignty entirely to external suppliers,' said Breton. 'Phase 2 is not simply a construction subsidy, but building a complete innovation chain from basic research and process development to talent reserve.'

Industry reacts positively, but concerns remain

The European Semiconductor Industry Association (ESIA) issued a statement on the same day welcoming Phase 2, believing the pilot line model can effectively share the tape-out costs of small design companies and promote ecosystem prosperity. Infineon's CEO stated: 'Europe needs its own nanoscale process verification platform; otherwise, the architectures we design can never be optimally realized.'

However, some analysts have pointed out concerns. First, the total size of €12 billion is smaller than Phase 1, while the cost of an advanced process pilot line often exceeds €10 billion, raising doubts about funding adequacy. Second, Europe is highly dependent on ASML for key equipment like EUV lithography, and ASML, a Dutch company, coordinates export controls with the US, limiting R&D freedom to some extent. Additionally, there is a need for policy coordination within the EU between the Chips Act and the European Green Deal—chip manufacturing's high water and energy consumption conflicts with carbon neutrality goals.

Impact on global semiconductor competition

Industry analysts believe that the EU Phase 2 will further intensify the global trend of 'regionalization' in semiconductors. Previously, the US has invested ~$52 billion through the CHIPS and Science Act, Japan has set up a ~3 trillion yen semiconductor fund, and South Korea has launched its 'K-Semiconductor Strategy.' The EU's additional commitment indicates that major economies all regard semiconductors as strategic infrastructure, pushing subsidy competition into 'deeper waters.'

For Singapore semiconductor companies, the EU's technological self-reliance may bring two aspects: in the short term, European demand for mature process and special process chips will still rely on Asia-Pacific foundries; but in the long term, Europe's open pilot line model will enhance local design capabilities, potentially weakening Singapore fabs' competitive advantage in high-end logic chips. On the other hand, Singapore still maintains strong competitiveness in semiconductor equipment, materials, and talent reserves, and could explore cooperation with Europe in advanced packaging and compound semiconductors.

Timeline and next steps

According to the plan, funds for Phase 2 will be disbursed in tranches from Q3 2026 to Q2 2029. The European Parliament and the Council of the EU must review and approve the relevant budget amendments by October 2026. Additionally, the EU will simultaneously promote the Foreign Subsidies Regulation, imposing 'technology result localization' requirements on chip companies building fabs in Europe to prevent them from using Europe solely as an assembly base.